研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD)SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的.
A compact drain current including the variation of barrier heights and carrier quantization in ultrathin-body and double-gate Schottky barrier MOSFETs （UTBDG SBFETs） is developed. In this model, Schrodinger＇s equation is solved using the triangular potential well approximation. The carrier density thus obtained is included in the space charge density to obtain quantum carrier confinement effects in the modeling of thin-body devices. Due to the quantum effects, the first subband is higher than the conduction band edge, which is equivalent to the band gap widening. Thus, the barrier heights at the source and drain increase and the carrier concentration decreases as the drain current decreases. The drawback of the existing models,which cannot present an accurate prediction of the drain current because they mainly consider the effects of Schottky barrier lowering （SBL） due to image forces,is eliminated. Our research results suggest that for small nonnegative Schottky barrier （SB） heights,even for zero barrier height, the tunneling current also plays a role in the total on-state currents. Verification of the present model was carried out by the device numerical simulator-Silvaco and showed good agreement.
