A sub-mA phase-locked loop fabricated in a 65nm standard digital CMOS process is presented. The impact of process variation is largely removed by a novel open-loop calibration that is performed only during start-up but is opened during normal operation. This method reduces calibration time significantly compared with its closed-loop counterpart. The dual-loop PLL architecture is adopted to achieve a process-independent damping factor and pole-zero separation. A new phase frequency detector embedded with a level shifter is introduced. Careful power partitioning is explored to minimize the noise coupling. The proposed PLL achieves 3. lps RMS jitter running at 1.6GHz while consuming only 0.94mA.
This paper describes the design of a low voltage differential signal （LVDS） transmitter and receiver with high speed and low power for CPU, LCD, FPGA, and other fast links. In the proposed transmitter, a stable reference and a common mode feedback circuit are integrated into the LVDS drivers, which enable the transmitter to tolerate variations of process, temperature, and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture that allows a 1.6Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3V,0. 18μm CMOS technology. The experimental results demonstrate that the transmitter and receiver reach 1.6Gb/s. The transmitter and receiver pad cells exhibit a power consumption of 35 and 6mW,respectively.
