Previous studies have indicated that data compression in wireless sensor networks is not always beneficial to energy conservation due to the additional computational energy costs. This work gives an energy-efficient arbitration mechanism that enhances the performance of compression algorithms by avoiding unnecessary energy losses. The adaptive compression arbitration system uses a new prediction modeling and adaptation. Tests show that the modeling method gives better predictions with the adaptive mechanism needing less data for modeling, which allows on-line prediction modeling instead of an off-line training process. Moreover, adaptive adjustments of the model parameters enable the system to keep good arbitration precision even as the data characteristics or applications change.
This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.
This paper describes a 12-bit, 40-MS/s pipelined A/D converter （ADC） which is implemented in 0.18-μm CMOS process drawing 76-mW power from 3.3-V supply. Multi-bit architectures as well as telescopic operational transconductance amplifiers （OTAs） are adopted in all pipeline stages for good power efficiency. In the first two stages, particularly, 3-bit/stage architectures are used to improve the ADC＇s linearity performance. The ADC is calibration-free and achieves a DNL of less than 0.51 LSB and an INL of less than 1 LSB. The SNDR performance is above 67 dB below Nyquist. The 80-dB SFDR performance is maintained within 1 dB for input frequencies up to 49 MHz at full sampling rate.
