To obtain a low-power and compact implementation of the advanced encryption standard （AES） S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. （1） Level-sensitive latches were inserted in data path to block the propagation Of the dynamic hazards, which lowered the power of data path circuit. （2） Operations of latches were controlled by latch controllers based on presented asynchronous sequence element： LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. （3） Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor （CMOS） process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty （ 11.7% ） compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelli-gent property （IP） embedded in the targeted systems such as wireless sensor networks （WSN）, smart-cards and radio frequency identification （RFID）.
The implementation of small size cryptography algorithm is a critical problem for wireless sensor network. A low cost compact intellectual property （IP） core of the entire advanced encryption standard （AES） algorithm for wireless sensor network is presented in this paper. A compact encryption and decryption system using only four sharing S-Boxes is obtained, employing sharing between the encryption and decryption processes. Our design proposes use of composite field data path for the SubBytes and InvSubBytes transformations. With an implementation of the AES block cipher with Virtex Ⅱ Pro FPGA using0.13μm and 90nm process technology, our area optimized consumes 16.8k equivalent gates. The speed of this implementation is also reduced to 0.45Gbits/s. Compared with previous implementations, our design achieves significant low-cost area with acceptable throughput.
易立华 Zou Xuecheng Liu Zhenglin Dan Yongping Zou Wanghui
This paper presents a new encryption embedded processor aimed at the application requirement of wireless sensor network （WSN）. The new encryption embedded processor not only offers Rivest Shamir Adlemen （RSA）, Advanced Encryption Standard （AES）, 3 Data Encryption Standard （3 DES） and Secure Hash Algorithm 1 （SHA - 1 ） security engines, but also involves a new memory encryption scheme. The new memory encryption scheme is implemented by a memory encryption cache （MEC）, which protects the confidentiality of the memory by AES encryption. The experi- ments show that the new secure design only causes 1.9% additional delay on the critical path and cuts 25.7% power consumption when the processor writes data back. The new processor balances the performance overhead, the power consumption and the security and fully meets the wireless sensor environment requirement. After physical design, the new encryption embedded processor has been successfully tape-out.
