In order to increase collection efficiency and eliminate image lag, multi n-type implants were introduced into the process of a pinned-photodiode. For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed, which expanded the vertical collection region. To reduce the image lag, a horizontal gradient doping concentration eliminating the potential barrier was also formed by multi n-type implants. The simulation result shows that the collection efficiency can be improved by about 10% in the long wavelength range and the density of the residual charge is reduced from 2.59 × 10^9 to 2.62 × 10^7 cm^-3.
A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.
Abs A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size. Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction. Further analysis of noise for incomplete charge transfer predicts the noise variation. The test pixels were fabricated in a specialized 0.18 #m CMOS image sensor process and two different processes of buried N layer implantation are compared. The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer. The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.
The charge transfer efficiency improvement method is introduced by optimizing the electrical potential distribution under the transfer gate along the charge transfer path. A non-uniform doped transfer transistor chan- nel is introduced to provide an ascending electrical potential gradient in the transfer transistor channel. With the adjustments to the overlap length between the R1 region and the transfer gate, the doping dose of the R1 region, and the overlap length between the anti-punch-through （APT） implantations and transfer gate, the potential barrier and potential pocket in the connecting region of transfer transistor channel and the pinned photodiode （PPD） are reduced to improve the electrical potential connection. The simulation results show that the percentage of residual charges to total charges drops from 1/10^4 to 1/10^7, and the transfer time is reduced from 500 to 110 ns. This means the charge transfer efficiency is improved.
To improve the full well capacity （FWC） of a small size backside illuminated （BSI） CMOS image sensor （CIS）, the effect of photodiode capacitance （Cpo） on FWC is studied, and a reformed pinned photodiode （PPD） structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e- to 6390e-, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency （QE） is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.
A single event upset （SEU） tolerant latch with a triple-interlocked structure is presented. Its self-recovery mechanism is implemented by using three pairs of guard-gates and inverters to construct feedback lines inside the structure. This latch effectively suppresses the effects of charge deposition at any single internal node caused by particle strikes. Three recently reported SEU-hardened latches are chosen and compared with this latch in terms of reliability. The potential problems that these three latches could still get flipped due to single event effects or single event effects plus crosstalk coupling are pointed out, which can be mitigated by this proposed latch. The SEU tolerance of each latch design is evaluated through circuit-level SEU injection simulation. Furthermore, discussions on the crosstalk robustness and some other characteristics of these latches are also presented.
A dynamic range extension scheme applied to a time delay integration （TDI） CMOS image sensor （CIS） is presented. Two types of pixels with higher and lower conversion gain are adopted in the pixel array, which are suitable for capturing images in low and high illumination respectively. By fusing the two kinds of pixels＇ output signals in the process of TDI accumulation, a high dynamic range image can be achieved. Compared with the traditional multiple integration technique, no photoelectrons generated during the exposure time are discarded by the reset operation, and thus a higher level of signal-to-noise ratio （SNR） can be retained. A prototype chip with an 8 × 8 pixel array is implemented in a 0.18 μm CIS process, and the pixel size is 15 × 15 μm2. Test results show that a 76 dB dynamic range can be achieved in 8-stage TDI mode, when the SNR boost can reach 7.26 dB at 90.8 lux.
This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC （Shanghai, China）. Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO＇s active chip-area is only smaller than 0.02 mm2.
