A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.
A12-Bit 40-MS/s pipelined analog-to-digital converter （ADC） incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise- and-distortion ratio, and -75.5-dB of total harmonic distortion （the first 5 harmonics included） while consuming 15.6-mW from a 1.2-V supply.
A single loop fourth-order delta-sigma modulator is presented for audio applications. A reconfigurable mechanism is adopted for two bandwidth-based modes （8 kHz/16 kHz）. Manufactured in the SM1C 0.13μm CMOS mixed signal process, the chip consumes low power （153.6 μW） and occupies a core area of 0.98×0.46 mm2. The presented modulator achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode, as well as a 90.2 dB SNR and 86 dB dynamic range in 8 kHz mode. The designed modulator shows a very competitive figure of merit among state-of-the-art low voltage modulators.
A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms （0.48-2000 Hz）. The chip is fabricated via a SMIC 0.18μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.
