Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting both ILP (Instruction Level Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading (SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%–61%longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0.4%～1%to most of the benchmarks we choose randomly.
＜正＞ Transient fault detection mechanism is added to simultaneous multithreading architecture. By exploiting bo...
DONG Lan, HU Ming-zeng, JI Zhen-zhou.CUI Guang-zuo, TANG Xin-min,HE FengDepartment of Computer Science and Engineering , Harbin Institute of Technology, Harbin 150001, Heilongjiang, China
