This paper presents a universal field programmable gate array（FPGA） programmable routing circuit,focusing primarily on a delay optimization.Under the precondition of the routing resource＇s flexibility and routability,the number of programmable interconnect points（PIP） is reduced,and a multiplexer（MUX） plus a BUFFER structure is adopted as the programmable switch.Also,the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit,respectively.All of the above features ensure that the whole FPGA chip is highly repeatable,and the signal delay is uniform and predictable over the total chip.Meanwhile,the BUFFER driver is optimized to decrease the signal delay by up to 5%.The proposed routing circuit is applied to the Fudan programmable device（FDP） FPGA,which has been taped out with an SMIC 0.18-μm logic 1P6M process.The test result shows that the programmable routing resource works correctly,and the signal delay over the chip is highly uniform and predictable.
A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX （multiplexer） is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm^2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.
A novel FPGA chip FDP2008 （Fudan Programmable Logic） has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX ＋ Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 ×30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.
本文主要研究高性能FPGA可编程逻辑单元中分布式RAM和移位寄存器两种时序功能的设计实现方法.运用静态Latch实现分布式RAM的写入同步,以降低对时序控制电路的要求;为克服电荷共享问题,提出通过隔断存储单元之间通路的方法实现移位寄存器.以含两个四输入LUT(Look Up Table)的多功能可编程逻辑单元为例,详细说明电路的设计思路以及实现方法.研究表明,本文提出的方法可以简化对时序控制电路的设计要求,克服电荷共享问题,减少芯片面积.
