Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.
The electron mobilities of 4, 7-diphenyl-1, 10-phenanthroline （BPhen） doped 8-hydroxyquinolinatolithium （Liq） at various thicknesses （50-300 nm） have been estimated by using space-charge-limited current measurements. It is observed that the electron mobility of 33 wt% Liq doped BPhen approaches its true value when the thickness is more than 200 rim. The electron mobility of 33 wt% Liq doped BPhen at 300 nm is found to be -5.2 × 10^-3 cm^2/（V.s） （at 0.3 MV/cm） with weak dependence on electric field, which is about one order of magnitude higher than that of pristine BPhen （3.4 × 10^-4 cm^2/（V.s）） measured by SCLC. For the typical thickness of organic light-emitting devices, the electron mobility of doped BPhen is also investigated.
