In view of the flaws of component-based software （CBS） reliability modeling and analysis, the low recognition degree of debugging process, too many assumptions and difficulties in obtaining the solution, a CBS reliability simulation process is presented incorporating the imperfect debugging and the limitation of debugging resources. Considering the effect of imperfect debugging on fault detec- tion and correction process, a CBS integration testing model is sketched by multi-queue muhichannel and finite server queuing model （MMFSQM）. Compared with the analytical method based on pa- rameters and other nonparametric approaches, the simulation approach can relax more of the usual reliability modeling assumptions and effectively expound integration testing process of CBS. Then, CBS reliability process simulation procedure is developed accordingly. The proposed simulation ap- proach is validated to be sound and effective by simulation experiment studies and analysis.
随着ULSI工艺步入深亚微米时代,处理器内部组合逻辑的瞬时故障敏感性迅速提高,文中在设计初期将硬件寄存器纠检错能力和系统软件检错能力纳入考虑,兼顾处理器内组合逻辑、时序逻辑两类部件,设计应用级"低代价锁步EDDI(Error Detection by Duplicated Instructions)"机制.创新如下:(1)提出基于概率论的故障漏检率量化估计方法,为纠检错与性能折中进行指导.以往的应用级检错机制在设计过程中并没有考虑到下层操作系统的检错能力,这会造成可靠性估计不足而带来性能损失.文中依照指令流经的部件将故障划分为不同子类,并将操作系统纳入考虑,提出基于概率论的故障漏检率量化估计方法,理论估计与故障注入结果拟合良好.(2)低代价锁步EDDI机制,结合硬件纠检错能力,兼顾处理器内组合逻辑和时序逻辑两类部件,大幅降低了性能代价.提出独特的低代价锁步指令复制规则,并通过编译链前端的寄存器分配,大幅减少了寄存器预留数,有效缓解了寄存器压力,降低了访存代价,提高了寄存器的性能.寄存器预留也保证了本机制无需修改编译器传参规则,无需重新编译系统库,提高了通用性.(3)采用单比特故障模型,基于SPARC体系结构,选取处理器中代表性部件:解码(DecoderUnit)单元、地址生成(Address GEN Unit)单元、算逻单元(ALU)进行故障注入,对低代价锁步EDDI实现代价进行详细评测.与全复制EDDI相比,低代价锁步EDDI仅以故障漏检率SDC(Silent Data Corruption)平均升高0.8%的代价,换取了动态执行指令数平均减少36.1%,执行时间平均降低35.2%的性能优势.
