针对一般聚类获得的码本缺乏判别性表示导致不能有效进行人体动作识别的问题,提出了一种新的自适应码本学习方法,该方法将判别式词袋(bag of words,Bo W)动作表示和自适应码本学习结合,增强了码本的表示能力和特征的判别性。为了有效求解非凸目标函数,提出基于轮换优化迭代方法,即固定码本更新判别矩阵,然后判别矩阵更新固定码本,直至满足终止迭代条件,该方法为自适应码本学习提供了技术支持。仿真实验采用KTH、Hollywood2、芭蕾、i3Dpost数据库进行判别比较,识别率比现有典型方法平均提高了4%左右,学习到的码本在特征空间中具有良好的判别性能。相比于基于光流、方向梯度直方图(histograms of oriented gradients,HOG)等方法,计算复杂度更低,实用性更好。
Recently, security in embedded system arises attentions because of modern electronic devices need cau- tiously either exchange or communicate with the sensitive data. Although security is classical research topic in world- wide communication, the researchers still face the problems of how to deal with these resource constraint devices and en- hance the features of assurance and certification. Therefore, some computations of cryptographic algorithms are built on hardware platforms, such as field program gate arrays （FPGAs）. The commonly used cryptographic algorithms for digital signature algorithm （DSA） are rivest-shamir-adleman （RSA） and elliptic curve cryptosystems （ECC） which based on the presumed difficulty of factoring large integers and the algebraic structure of elliptic curves over finite fields. Usu- ally, RSA is computed over GF（p）, and ECC is computed over GF（p） or GF（2P）. Moreover, embedded applications need advance encryption standard （AES） algorithms to pro- cess encryption and decryption procedures. In order to reuse the hardware resources and meet the trade-off between area and performance, we proposed a new triple functional arith- metic unit for computing high radix RSA and ECC operations over GF（p） and GF（2P）, which also can be extended to support AES operations. A new high radix signed digital （SD） adder has been proposed to eliminate the carry propagations over GF（p）. The proposed unified design took up 28.7% less hardware resources than implementing RSA, ECC, and AES individually, and the experimental results show that our proposed architecture can achieve 141.8 MHz using approxi- mately 5.5k CLBs on Virtex-5 FPGA.
硬件实现的SMS4加密算法计算过程中容易出现故障,为防止攻击者利用故障信息进行故障攻击从而破解SMS4算法,提出一种针对SMS4算法的故障检测方案。该方案首先分析了硬件实现的SMS4算法出现故障的位置及其影响,然后在关键路径上建立了3个检测点,通过实时监测检测点来定位算法执行过程中出现的故障。一旦成功检测到故障,立即重新执行算法以保证攻击者难以获取有效的故障信息。将提出的方案和原无故障检测的算法分别在Xilinx公司的Virtex-7和Altera公司的Cyclone II EP2C35F76C6两个现场可编程门阵列(FPGA)上综合实现,在Virtex-7上,提出的带故障检测的方案比原算法占用逻辑资源增加30%,吞吐量相当;在EP2C35F76C6上比原算法增加0.1%的硬件资源,吞吐量达到原来的93%。实验结果表明,在尽量不影响吞吐量的前提下,提出的方案占用硬件资源小,并且可以有效地检测出故障,从而避免SMS4算法受到故障攻击。
