A new double gate SOI LDMOS with a step doping profile in the drift region is proposed. The structure is characterized by one surface gate and another embedded gate under the P-body region. The broadened current flow path and the majority carrier accumulation layer on the side wall of the embedded gate reduce the specific on-resistance （Ron, sp）. The electric field distribution is improved due to the embedded gate and step doping profile, resulting in a high breakdown voltage （BV） and low Ron, sp. The influences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOI LDMOS.
A new lateral insulated-gate bipolar transistor（LIGBT） with a SiO_2 shielded layer anode on SOI substrate is proposed and discussed.Compared to the conventional LIGBT,the proposed device offers an enhanced conductivity modulation effect due to the SiO_2 shielded layer anode structure which can be formed by SIMOX technology.Simulation results show that,for the proposed LIGBT,during the conducting state,the electron-hole plasma concentrations in the n-drift region are several times larger than those of the conventional LIGBT;the conducting current is up to 37% larger than that of the conventional one.The enhanced conductivity modulation effect by SiO_2 shielded layer anode does not sacrifice other characteristics of the device,such as breakdown and switching,but is compatible with other optimized technologies.
A new SO1 high-voltage device structure with nonuniform thickness drift region （n-uni SOl） and its optimiza- tion design method are proposed. Owing to the nonuniform thickness drift region, the electric field in the SOl layer is modulated and the electric field in the buried layer is enhanced, resulting in an enhancement of breakdown voltage. An analytical model taking the modulation effect into account is presented to optimize the device structure. Based on the analytical model, the dependencies of the electric field distribution and breakdown voltage on the device parameters are investigated. Numerical simulations support the analytical model. The breakdown voltage of the n-uni SOl LDMOS with n = 3 is twice as high as that of a conventional SO1 while its on-resistance maintains low.
A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.
A new NI （n^＋ charge islands） high voltage device structure based on E-SIMOX （epitaxy-the separation by implantation of oxygen） substrate is proposed. It is characterized by equidistant high concentration n＋-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field （Ev） are located in the spacing of two neighboring n^＋-regions on the interface by the force from lateral electric field （EL） and the compositive operation of Coulomb＇s forces with the ionized donors in the undepleted n^＋-regions. This effectively enhances the electric field of dielectric buried layer （EI） and increases breakdown voltage （VB）. An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology （E-SIMOX）.
