This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signal-flow,complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement,and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.
A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming （MLP） problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.
We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first （LFF） principle,we simulate a manual packing process in which the concept of placement by stages is introduced to reduce the overall evaluation complexity. The complexity of the proposed algorithm is （N1 ＋ N2 ） × O（ n^2 ） ＋ N3× O（n^4lgn） ,where N1, N2 ,and N3 denote the number of modules in each stage, N1 ＋ N2 ＋ N3 = n, and N3〈〈 n. This complexity is much less than the original time complexity of O（n^5lgn）. Experimental results indicate that this approach is quite promising.
