A new incremental placement algorithm C-ECOP for standard cell layout is presented to reduce routing congestion.It first estimates the routing congestion through a new routing model.Then,it formulates an integer linear programming (ILP) problem to determine cell flow direction and to avoid the conflictions between adjacent congestion areas.Experimental results show that the algorithm can considerably reduce routing congestion and preserve the performance of the initial placement with high speed.
A global routing algorithm with performance optimization under multi constraints is proposed,which studies RLC coupling noise,timing performance,and routability simultaneously at global routing level.The algorithm is implemented and the global router is called CEE Gr.The CEE Gr is tested on MCNC benchmarks and the experimental results are promising.
A new approach of incremental placement approach is described.The obtained timing information drives an efficient net-based placement technique,which dynamically adapts the net weights during successive placement steps.Several methods to combine timing optimization and congestion reducing together are proposed.Cells on critical paths are replaced according to timing and congestion constraints.Experimental results show that our approach can efficiently reduce cycle time and enhance route ability.The max path delay is reduced by 10% on an average afterincremental placement on wirelength-optimized circuits.And it achieves the same quality with a high speed up compared to timing driven detailed placement algorithm.
As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.
