在基于数字信号处理的粒子探测器读出电路设计中,模数转化器(analog to digital converter,ADC)是一个关键的模块。ADC的采样率和精度是限制探测系统达到最佳噪声性能的主要参数。基于Matlab的Simulink环境建立了粒子探测器读出电路中ADC的仿真模型,并通过Matlab仿真验证了模数转化器的采样速度、精度对系统噪声的影响,给出了在基于数字信号处理的粒子探测器读出电路设计中,模数转换器的参数设计方案。
A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
A low power digital operational transconductance amplifier （OTA） was developed for low voltage switched capacitor applications. The OTA has a high slew rate （SR） and a large open loop gain with a dif- ferential pseudo-two-stage Class-AB structure. A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal （MIM） capacitor to reduce the fabrication cost. Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output terminal, this digital differential pseudo-two-stage Class-AB OTA realized in 0.13-μm technology achieves a 63.5-dB DC gain and a 0.83-V output swing. The slew rate is ±16.29V/μs and the total power dissipation is only 82 μW.
