A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage （BV） of conventional super junction-LDMOS. The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance. Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars. In addition, the proposed device is compatible with smart power technology.
The lateral super junction （SJ） power devices suffer the substrate-assisted depletion （SAD） effect, which breaks the charge balance of SJ resulting in the low breakdown voltage （BV）. A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET （SJ-LDMOS）. High density interface charges enhance the electric field in the buried oxide （BOX） layer to increase the block voltage of BOX, which suppresses the SAD effect to achieve the charge balance of SJ. In order to obtain the linear enhancement of electric field, SO1 SJ-LDMOS with trenched BOX is presented. Because the trenched BOX self-adaptively collects holes according to the variable electric field strength, the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need. As a result, the charge balance between N and P pillars of SJ is achieved, which improves the BV of SJ-LDMOS to close that of the idea SJ structure.
A new super junction LDMOST structure that suppresses the substrate-assisted depletion effect is designed with an n^＋-floating layer embedded in the high-resistance p-type substrate by implanting phosphor or arsenic. This effect results from a charge imbalance between the n-type and p-type pillars when the n-type pillars are depleted by p-type substrate. The high electric field around the drain is reduced by the n^＋-floating layer due to the REBULF effect,which causes the redistribution of the bulk electric field in the drift region,and thus the substrate supports more biases. The new structure features high breakdown voltage, low on-resistance,and charge balance in the drift region.
In this paper, we propose a novel low on-resistance Super Junction （S J） Lateral Double-diffusion MOSFET （LDMOST） which has split p column structures with rated voltage of 60-100V. The key feature of this new structure is that the split p column super junction primarily provides the low on-resistance path and it just locates at the surface of the drift region rather than the entire drift region. The manufacturing process of the device is relatively simple and is compatible with the Bi-CMOS process. Three dimension device simulations indicate that this structure can achieve a low specific on-resistance of 11.5 mΩ·cm^2 at a gate voltage of 5 V compared with 27.7 mΩ·cm^2 for the conventional LDMOST at the breakdown voltage of 80V.
