The requirement of a large number of electronic channels poses a big challenge to the further applications of Micro-pattern Gas Detectors （MPGDs）. By using the redundancy that at least two neighboring strips record the signal of a particle, a novel method of encoded multiplexing readout for MPGDs is presented in this paper. The method offers a feasible and easily-extensible way of encoding and decoding, and can significantly reduce the number of readout channels. A verification test was carried out on a 5 cm×5 cm Thick Gas Electron Multiplier （THGEM） detector using a 8 keV Cu X-ray source with 100um slit, where 166 strips were read out by 21 encoded readout channels. The test results show good linearity in its position response, and the spatial resolution root-mean-square （RMS） of the test system is about 260um. This method has potential to build large area detectors and can be easily adapted to other detectors similar to MPGDs.
Background:PandaX-III is aimed to search for neutrinoless double beta decay of 136Xe at China Jinping Underground Laboratory.To test various design features of PandaX-III detector,a prototype TPC with 20 kg Xe containing inside is built.Purpose:Front-end boards installed inside the waterproof vessel integrate charge of Micromegas signal,digitize signal waveform and send data packet to back-end board.Frontend boards receive synchronous information(global clock,global trigger,etc.),as well as command messages from back-end board.In order to satisfy the requirement of high data throughput and multiple types of synchronous data transmission,we propose an optical fiber link to communicate between front-end board and back-end board.Methods:Communication of serial transmission is performed using FPGA-based gigabit transceiver with a 1 Gbit/s point-to-point speed.A dedicated user-defined protocol is implemented for various kinds of data transmission.Results:To validate the performance of this link,bit error rate and eye diagram were tested.Preliminary joint test with detector was conducted in Shanghai.All test results showed sufficient data bandwidth and stable performance.Conclusion:To satisfy the requirement for data transmission between front-end board and back-end board in PandaX-III TPC detector readout,an FPGA-based gigabit serial link is designed and tested.This design shows good performance and will be applied to the R&D of PandaX-III TPC.
Cheng LiChangqing FengJianing DongDanyang ZhuShubin LiuQi An
Up to now, the wave union method can achieve the best timing performance in FPGA-based TDC designs. However, it should be guaranteed in such a structure that the non-thermometer code to binary code （NTH2B） encoding process should be finished within just one system clock cycle. So the implementation of the NTH2B encoder is quite challenging considering the high speed requirement. Besides, the high resolution wave union TDC also demands that the encoder convert an ultra-wide input code to a binary code. We present a fast improved fat tree encoder （IFTE） to fulfill such requirements, in which bubble error suppression is also integrated. With this encoder scheme, a wave union TDC with 7.7 ps RMS and 3.8 ps effective bin size was implemented in an FPGA from Xilinx Virtex 5 family. An encoding time of 8.33 ns was achieved for a 276-bit non-thermometer code to a 9-bit binary code conversion. We conducted a series of tests on the oscillating period of the wave union launcher, as well as the overall performance of the TDC; test results indicate that the IFTE works well. In fact, in the implementation of this encoder, no manual routing or special constraints were required; therefore, this IFTE structure could also be further applied in other delay-chain-based FPGA TDCs.
A scalable readout system （SRS） is designed to provide a general solution for different micro-pattern gas detectors in various applications. The system mainly consists of three kinds of modules： the ASIC card, the adapter card and the front-end card （FEC）. The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the adapter, has field-programmable gate array （FPGA）-based reconfigurable logic and I/O interfaces, allowing users to choose different ASIC cards and adapters for different experiments, which expands the system to various applications. The FEC transfers data through Gigabit Ethernet protocol realized by a TCP processor （SiTCP） IP core in FPGA. By assembling a flexible number of FECs in parallel through Gigabit Ethernet, the readout system can be tailored to specific sizes to adapt to the experiment scales and readout requirements. In this paper, two kinds of multi-channel ASIC chip, VA140 and AGET, are applied to verify the scalability of this SRS architecture. Based on this VA140 or AGET SRS, one FEC covers 8 ASIC （VA140） cards handling 512 detector channels, or 4 ASIC （AGET） cards handling 256 detector channels, respectively. More FECs can be assembled in crates to handle thousands of detector channels.
